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Message: [QUOTE="Shamiso, post: 92534, member: 160"] CXMT says its G5 DRAM platform entered mass production on September 20 with an 11.95-nanometer active-area half-pitch and 24-gigabit LPDDR5X dies. Those numbers sound simple until you try to compare them with the process labels used by Samsung, SK hynix, or Micron. G5 is not CXMT’s first LPDDR5X production run. The company had already moved 8,533 and 9,600 Mbps LPDDR5X products into mass production in 2025, so the new announcement is really about a denser manufacturing platform and larger dies rather than CXMT suddenly learning how to make mobile DRAM. [HEADING=2]CXMT’s G5 platform changes the manufacturing baseline[/HEADING] CXMT reports an active-area half-pitch of 11.95 nm, a 45-to-1 capacitor aspect ratio, and a core cell-array height of 6,762 nm. It also says the platform uses a DRAM-specific high-k metal gate process and a digital-twin system spanning design, tape-out, manufacturing, and yield maintenance. The interesting bit is the patterning route. G5 uses [B][URL='https://patents.google.com/patent/US10910381B2/en']self-aligned quadruple patterning for DRAM[/URL][/B], a method that can create tighter repeated structures by building them through several self-aligned spacer steps instead of depending on one lithography exposure to print the final pitch. More steps also mean more places for variation to creep in. Small errors in deposition thickness, etch behavior, or the original mandrel can distort spacing across the final pattern, so reaching a small pitch in a lab is one problem while holding it across production wafers is another. CXMT’s announcement matters because it says G5 has crossed into mass production rather than remaining a development vehicle. Still, the company did not publish monthly wafer starts, independently audited yield, defect density, or shipment volumes, so the public data establishes a manufacturing claim without telling you how much saleable output the line produces. [HEADING=2]The 11.95 nm figure needs careful reading[/HEADING] An 11.95 nm active-area half-pitch is a physical measurement inside the DRAM memory array. It is not automatically equivalent to an “11.95 nm process node” in the way people casually talk about CPU or GPU manufacturing, because modern node names do not map cleanly to one shared physical dimension. Even comparisons between memory makers need care. One company may advertise a generation label such as 1c, another may discuss a half-pitch, and neither label alone tells you transistor dimensions, capacitor geometry, peripheral circuitry, power behavior, or manufacturing cost. Useful, but easy to overread. CXMT also reports a 45-to-1 capacitor aspect ratio. DRAM capacitors have to stay electrically useful while their footprint keeps shrinking, so manufacturers build increasingly tall, narrow structures rather than simply making every dimension smaller at once. The 6,762 nm core cell-array height belongs in the same bucket. It is useful process information, but it is not a universal score that lets you rank one DRAM maker above another without knowing the rest of the layout and electrical behavior. This distinction matters when people connect G5 with [B][URL='https://goldmidi.com/community/threads/cxmt-prepares-beijing-nand-expansion-beyond-dram.77891/']CXMT’s reported move into NAND flash[/URL][/B]. Strong DRAM process control is relevant evidence of manufacturing capability, but NAND uses a different structure, process flow, qualification path, and scaling problem. [HEADING=2]Gross dies per wafer are not production yield[/HEADING] CXMT says G5 increases die per wafer by at least 50 percent over its fourth-generation platform. The fine print matters because the figure is a gross die count normalized to an 8Gb density baseline, not a statement that every commercial product now delivers 50 percent more working chips. Normalization is doing real work here. Comparing both generations as 8Gb-equivalent dies strips out the simple capacity difference between products, so a new 24Gb part cannot look better merely because each die stores three times as many bits as an 8Gb reference. Gross die per wafer counts how many die positions can physically fit before electrical testing sorts good silicon from bad. Smaller dies usually help this number, but saleable output still depends on defect density, redundancy, binning, packaging losses, and whether each die meets its voltage, speed, and power targets. Yield is the missing number. A denser process can put more theoretical dies on one wafer while still producing fewer good parts than expected if defect rates rise, and the economics only improve once enough of those extra positions survive testing. The two new LPDDR5X products contain 24Gb per die, which equals 3GB of raw capacity on each die. CXMT offers them in 496-ball and 245-ball packages for phones and portable electronics, but the launch material does not disclose a new headline data rate for these G5 parts. A package choice also tells you less than it seems. Ball count describes the physical interface and package layout, not the number of gigabytes in a finished phone, which depends on how dies are combined and what configuration the device maker buys. [/QUOTE]

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