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Labrish
Nyuuz
CXMT taps Haesung DS panel process for DDR6 race
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[QUOTE="Queen, post: 89966, member: 27"] CXMT is already rigging its DDR6 playbook with a brand-new panel-based manufacturing process, and Samsung and SK Hynix haven't even locked in their approach yet. The DRAM shortage is handing the Chinese underdog a golden window. Haesung DS, a package substrate maker, just joined CXMT's supply chain and cleared DDR5 qualification tests, positioning itself for the multi-layer designs DDR6 demands. Here's the thing. DDR4 and DDR5 used a cheap Reel-to-Reel method with low-layer substrates. DDR6 stacks way more circuit layers, and that old process tanks in profitability once complexity ramps. The panel method sidesteps that mess. CXMT's DDR5 still trails SK hynix at matched speeds, but the company is betting on leaping ahead before commercialization hits. And get this. Apple is reportedly testing CXMT's memory chips and eyeing a partnership, which is a massive credibility boost for a firm most people wrote off. The DRAM shortage made CXMT relevant not through superior tech but through sheer supply availability. Mass production timing remains unconfirmed, but with a 2028-to-2029 target floating around, the pressure is absolutely on. [/QUOTE]
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Nyuuz
CXMT taps Haesung DS panel process for DDR6 race
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