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[QUOTE="Munyaradzi Mafaro, post: 35611, member: 636"]
TSMC showcased new packaging technologies at its Technology Symposium alongside chip announcements. The company plans to release improved versions of its current packaging methods. These advanced packages help companies like NVIDIA work around the limits of Moore's Law. Modern packaging places multiple chips on one wafer, delivering huge performance gains compared to traditional methods.

The company will introduce a mainstream CoWoS version with a 9.5x reticle size that fits 12 memory stacks. Production begins in 2027 for this option. Current CoWoS packages use a 5.5x reticle size. The jump to 9.5x marks major progress for the Taiwanese chip maker. TSMC aims to replace these packages with System-on-Wafer technology later. The firm already shared details about this new approach earlier.

SoW technology will handle up to 40 times the reticle limit with sixty memory stacks. This makes it perfect for artificial intelligence systems that need large clusters. TSMC also mentioned a variant called SoW-X during the event. The company claims SoW-X delivers 40 times more computing power than current CoWoS packages. Both SoW versions should enter mass production around 2027. TSMC already leads the advanced chip packaging market. The company plans to keep its top position with these new solutions.
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