Global Unichip Corp. has made a big breakthrough with its new computer chip technology. They just became the first company ever to release UCIe PHY silicon that runs at 32 Gbps per lane. This speed reaches the highest level possible under current UCIe rules. The chip transfers data at an amazing 10 trillion bits per second for every millimeter of edge space. GUC built this using TSMC's advanced N3P process and CoWoS packaging tech for AI systems, fast computers, new processors, and network equipment.
The test version connects several chips through a special CoWoS base layer. These chips have connectors facing different directions—north-south and east-west. Tests show these connections work great at 32 Gbps with clear signal patterns. GUC plans to finish all their testing soon and will share the complete results next quarter. They created special bridges that let AXI, CXS, and CHI systems talk to each other using the UCIe Streaming Protocol. These bridges pack lots of data, use little power, send information quickly, and control data flow well.
Their design makes it easy to switch from single-chip systems to multi-chip setups. The bridges can change voltage and frequency on each chip separately without stopping data flow. GUC added special monitoring features from proteanTecs that check the signal quality during operation. This happens without interrupting normal work. Each connection path gets monitored individually, catching power problems and signal issues right away. The system finds potential bumps and trace defects early and fixes problems by switching to backup connections.
GUC keeps pushing ahead with faster tech that uses less electricity. In late 2024, they finished designing their second UCIe version running at 40 Gbps per lane. This newer model uses half the power thanks to Adaptive Voltage Scaling. A face-up model designed for 3D stacking with silicon connections should be ready very soon. They have already started work on their third generation, running at 64 Gbps per lane, scheduled for completion later this year. All these products work with different types of CoWoS and future TSMC SoW-X platforms.
The test version connects several chips through a special CoWoS base layer. These chips have connectors facing different directions—north-south and east-west. Tests show these connections work great at 32 Gbps with clear signal patterns. GUC plans to finish all their testing soon and will share the complete results next quarter. They created special bridges that let AXI, CXS, and CHI systems talk to each other using the UCIe Streaming Protocol. These bridges pack lots of data, use little power, send information quickly, and control data flow well.
Their design makes it easy to switch from single-chip systems to multi-chip setups. The bridges can change voltage and frequency on each chip separately without stopping data flow. GUC added special monitoring features from proteanTecs that check the signal quality during operation. This happens without interrupting normal work. Each connection path gets monitored individually, catching power problems and signal issues right away. The system finds potential bumps and trace defects early and fixes problems by switching to backup connections.
GUC keeps pushing ahead with faster tech that uses less electricity. In late 2024, they finished designing their second UCIe version running at 40 Gbps per lane. This newer model uses half the power thanks to Adaptive Voltage Scaling. A face-up model designed for 3D stacking with silicon connections should be ready very soon. They have already started work on their third generation, running at 64 Gbps per lane, scheduled for completion later this year. All these products work with different types of CoWoS and future TSMC SoW-X platforms.
