Intel prepares to restore AVX 10.2 512-bit instruction support across future processor generations. The company's oneDNN patch version 3.9-rc reveals compatibility plans for upcoming Xeon Diamond Rapids and Core Nova Lake processors. This marks a significant return after Intel removed AVX-512 capabilities from consumer chips following Rocket Lake.
The removal occurred because hybrid architectures created compatibility problems between performance and efficiency cores. Performance cores supported the instructions while efficiency cores did not, leading Intel to disable the feature entirely. Heat generation and power consumption also contributed to this decision.
Nova Lake maintains hybrid design principles while integrating AVX 10.2 instruction sets. Coral Rapids processors will reintroduce simultaneous multithreading alongside the restored vector capabilities. The patch also mentions Xe3 graphics architecture improvements, which Panther Lake processors will feature as integrated graphics solutions.
These developments position Intel to compete more effectively against AMD's current offerings that provide both features efficiently.
The removal occurred because hybrid architectures created compatibility problems between performance and efficiency cores. Performance cores supported the instructions while efficiency cores did not, leading Intel to disable the feature entirely. Heat generation and power consumption also contributed to this decision.
Nova Lake maintains hybrid design principles while integrating AVX 10.2 instruction sets. Coral Rapids processors will reintroduce simultaneous multithreading alongside the restored vector capabilities. The patch also mentions Xe3 graphics architecture improvements, which Panther Lake processors will feature as integrated graphics solutions.
These developments position Intel to compete more effectively against AMD's current offerings that provide both features efficiently.
