AMD plans to replace its die-to-die interconnect technology with Zen 6 processors after using the same approach since Zen 2. The company currently relies on SERDES PHYs that convert parallel traffic to serial bitstreams for communication between dies. This method creates energy overhead through clock recovery and encoding while adding latency to data transfers.
Strix Halo APUs demonstrate AMD's new strategy using TSMC's InFO-oS technology with redistribution layers. The updated design employs short parallel wires placed between dies rather than serial conversion processes. High Yield researchers identified this change by spotting rectangular pad fields and missing SERDES blocks on Strix Halo chips.
The parallel wire approach reduces both power consumption and latency while enabling higher bandwidth through additional ports across the CPU fabric.
Strix Halo APUs demonstrate AMD's new strategy using TSMC's InFO-oS technology with redistribution layers. The updated design employs short parallel wires placed between dies rather than serial conversion processes. High Yield researchers identified this change by spotting rectangular pad fields and missing SERDES blocks on Strix Halo chips.
The parallel wire approach reduces both power consumption and latency while enabling higher bandwidth through additional ports across the CPU fabric.
