Intel is ripping apart its chips because, apparently, glue is the future. Kernel patches exposed that Diamond Rapids Xeon processors will physically isolate compute tasks from memory management by using distinct tiles. The Core Building Block supposedly handles the math, while a separate Integrated I/O and Memory Hub takes care of the data flow. Leaks indicate the memory controller sits on the base layer alongside support for PCIe Gen6 connectivity.
Code divers noticed the architecture uses unique discovery tables for each die instead of a global list. The system apparently finds performance monitors through different pathways depending on whether it checks the compute or memory sections. Engineers switched the free-running counters to a memory-mapped input-output setup rather than the old standard.
Gossip suggests these power-hungry monsters might run up to two hundred fifty-six Panther Cove cores on the 18A node. The LGA 9324 socket allegedly draws six hundred fifty watts to feed the beast.
Code divers noticed the architecture uses unique discovery tables for each die instead of a global list. The system apparently finds performance monitors through different pathways depending on whether it checks the compute or memory sections. Engineers switched the free-running counters to a memory-mapped input-output setup rather than the old standard.
Gossip suggests these power-hungry monsters might run up to two hundred fifty-six Panther Cove cores on the 18A node. The LGA 9324 socket allegedly draws six hundred fifty watts to feed the beast.
