AMD plans to replace SERDES interconnects with parallel wiring for future Zen 6 processors, and evidence appears in recent Strix Halo APU designs. The company will route data through multiple parallel traces rather than serialize information across chiplet boundaries. Photographs reveal rectangular pad arrays where SERDES blocks previously occupied die edges, and the packaging matches TSMC's InFO-oS specifications for dense inter-die connections.
The parallel approach eliminates serialization steps that add latency, and the design reduces power consumption while freeing silicon area. Engineers can position compute dies closer to memory controllers without large interface blocks between components. The method faces obstacles with signal quality across many traces, but wider buses provide more bandwidth than traditional links. Manufacturing precision becomes critical because defects affect multiple data lanes simultaneously.
The parallel approach eliminates serialization steps that add latency, and the design reduces power consumption while freeing silicon area. Engineers can position compute dies closer to memory controllers without large interface blocks between components. The method faces obstacles with signal quality across many traces, but wider buses provide more bandwidth than traditional links. Manufacturing precision becomes critical because defects affect multiple data lanes simultaneously.
