AMD just whipped out a stupidly high core count CPU to feed its AI rigs. The CEO showed off a new EPYC server chip called Venice, which is meant to be the brains for their upcoming Helios AI server racks packed with Instinct MI455X graphics cards. Each compute node would use one of these monster CPUs to manage several GPUs. The wild spec is the core count, with Venice supposedly packing 256 cores and 512 threads into a single package. They are getting there by using eight separate compute chiplets made on a 2-nanometer process, each holding 32 cores based on the Zen 6 architecture. This is a different layout from the current EPYC chips.
A big question remains about what kind of cores are inside those chiplets. They might be full-power versions for higher speeds, or they could be denser, slower cores meant just to keep data flowing to the accelerators. AMD did not clarify that part. The memory setup is getting a huge boost to prevent bottlenecks, with support for sixteen channels of DDR5 RAM. To handle all that, the processor package uses two input-output dies instead of one. This should help with wiring and spreading out the memory controllers.
Connectivity is also getting expanded, with more PCIe and CXL lanes for extra gear like data processing units and super-fast network cards. The whole point of Venice in the Helios rack is to eliminate slowdowns. It needs to provide enough bandwidth for memory and data movement to stop the powerful GPUs from sitting around waiting. The success of this system hinges on the CPU keeping everything fed across many servers.
A big question remains about what kind of cores are inside those chiplets. They might be full-power versions for higher speeds, or they could be denser, slower cores meant just to keep data flowing to the accelerators. AMD did not clarify that part. The memory setup is getting a huge boost to prevent bottlenecks, with support for sixteen channels of DDR5 RAM. To handle all that, the processor package uses two input-output dies instead of one. This should help with wiring and spreading out the memory controllers.
Connectivity is also getting expanded, with more PCIe and CXL lanes for extra gear like data processing units and super-fast network cards. The whole point of Venice in the Helios rack is to eliminate slowdowns. It needs to provide enough bandwidth for memory and data movement to stop the powerful GPUs from sitting around waiting. The success of this system hinges on the CPU keeping everything fed across many servers.
